The present invention relates to a solid-state imaging apparatus and a semiconductor device, and is suitably usable in, for example, a solid-state imaging apparatus and a semiconductor device both equipped with successive comparison type A/D converters.
A digital camera captures a subject and forms an image on a solid-state imaging apparatus as an optical image. The solid-state imaging apparatus is roughly divided into CCD (Charge Coupled Device) and CMOS (Complementary Metal Oxide Semiconductor) image sensors. From the viewpoint of attaining high performance of the camera, a CMOS image sensor easy to be equipped with a CMOS circuit for image processing as a peripheral circuit is increasingly attracting attention. As the CMOS image sensor, there are known an analog image sensor and a digital image sensor. Although each of them has its merits and demerits, there are high expectations for the digital image sensor in terms of a data processing speed.
In the digital image sensor, an A/D (Analog-to-Digital) converter is provided in each column of a pixel array. There has been disclosed in, for example, a Non-Patent Document 1, a digital image sensor using successive comparison type A/D converters. In this type of digital image sensor, a pixel array including a plurality of pixels disposed in a plurality of rows and a plurality of columns is provided, and an analog pixel signal is outputted to a column signal line corresponding to each column.
The successive comparison type A/D converters are provided in each column and respectively equipped with an S/H (Sample-and-Hold) circuit, a D/A (Digital-to-Analog) converter, a comparator, and a successive approximation register. The voltage of the analog pixel signal and the output voltage of the D/A converter are compared with each other. The successive approximation register performs binary search control according to its comparison result in such a manner that the output voltage of the D/A converter approximates the analog pixel signal. A control code of the successive approximation register when the output signal of the D/A converter approximates the analog pixel signal is outputted as a digital pixel signal.
By executing A/D conversions of two steps using a plurality of subrange regions, the area of the D/A converter has been reduced and further differential nonlinearity (DNL) has been improved. In the two-step A/D conversions, a coarse A/D conversion is performed on the subrange regions by the binary search. The remaining fine A/D conversion is performed on the selected subrange region by a general successive comparison using a binary-weighted capacitor array, using a reference voltage for giving the region. Further, since the settling time of the reference voltage becomes a problem in a solid-state imaging apparatus provided with a plurality of A/D converters in parallel, the stabilization of the reference voltage is achieved by coupling to each external decouple capacitor.
Further, there has been disclosed in a Non-Patent Document 2, a circuit which corrects a settling error of a reference voltage of a successive comparison type A/D converter. A D/A converter which generates a comparison voltage is provided with a redundant capacitor to execute a redundant successive comparison operation, thereby enabling correction of the settling error by digital signal processing.